We are looking for a brilliant Verification engineer that can quickly join a most promising and exciting start up company in Poleg / Haifa at its very early stages to take a part in and contribute in developing a complex and challenging chip.
דרישות:
• Above 3 years of chip design development and verification
• Deep familiarity with verification and debug methodologies and tools
• Knowledgeable in Specman or system Verilog languages
• Vast knowledge of verification flow – (block level and full chip verification)
• Familiarity with one or more of the following verification environments: VMM, OVM, UVM
• Familiarity with formal verification - advantage