You are:
· A team player with good communication skills
· Innovator, brings out of the box solutions
You will:
· Be responsible for RTL design of new blocks and legacy blocks, chip integration, block level and top level verification, RTL simulations and gate level simulations
· work with architecture and system groups for design specification definitions and implementation impacts
· Handling block level synth, lint, integrating and supporting DFT structures
· Support BE team during chip implementation for design related topics as well as production and validation teams tests ramp up"
· You hold a bachelor's degree in Electrical Engineering or Computer Engineering
· You have at least 5 years of experience as a VLSI front-end engineer
· You are experience with Verilog and System Verilog design coding
· You must be fluent in English